The challenge of Digital Engineering

Digital Engineering is a key part of Digital Transformation. However, for many organizations, it is a bit of an enigma in terms of business value. Part of the problem is a lack of imagination that cuts through marketing hype to focus on how exactly the enterprise can benefit from it. This blog explores how an innovative approach to Digital Engineering can help to disrupt the design of complex electronic systems by decreasing design time and costs, reducing functional product failures, and increasing manufacturing yields.

What if…

Today, Integrated Circuits (ICs) and Printed Circuit Boards (PCBs) are designed separately on different timelines by multiple teams using different methodologies and tools. IC designs lead, and PCB designs follow because PCBs depend on how ICs are designed and packaged as electronic components. But what if silicon chips, IC packages, and PCBs could be designed simultaneously and collaboratively in the context of the same system requirements, ensuring optimum system performance? What if that also reduced the overall product design time and minimized product performance risks?

The emergence of the chiplet-driven 3D IC packages, together with the emergence of PLM-managed digital thread, makes that possible, but only if digital thread traceability evolves to encompass:

  • Model Based System Engineering (MBSE)
  • IC design methodologies (silicon chips and IC packages)
  • PCB design methodologies
  • Simulation and Process Data Management (SPDM) solutions

The amazing chiplets

Chiplet-driven 3D IC is a disruptive silicon design and packaging technology for creating ever more powerful IC components. These ICs are often called a System in Package (SiP). Chiplets and SiPs together enable packaging more transistors in less space, delivering ever-rising performance and ever-more complex functionality. They also result in lower design costs, faster design cycles, and higher manufacturing yields than the more traditional approach of System on Chip (SoC), as highlighted by TrendForce.

SiPs are created by integrating independently designed and manufactured small and function-specific silicon chiplets. Reused and newly designed chiplets are arranged next to each other and/or above the other and are interconnected within a single physical IC package. SoCs, on the other hand, are created with a single monolithic and large silicon chip that encompasses all required functionality and is placed within a single physical IC package.

Striking similarities between interposer and PCB

One critical technological innovation of SiP is the silicon interposer substrate with Through Silicon Vias (TSVs). Its function is to provide electrical connections between chiplets. This is similar to the structure of the High-Density Interconnect Printed Circuit Board (HDI PCB), except for scale, substrate material, and manufacturing process. In both cases, horizontal connections are imaged with copper on substrate layers, and vertical connections are copper-filled vias through substrate layers. Vias also connect to bums/pins of the chiplets/components. This way, chiplets in SiP can be electrically interconnected like components on PCB.

These similarities between SiP and PCB physical interconnects are not lost on the industry as exemplified by proposals to eliminate PCBs altogether (here). Absolutely fascinating!

Performance optimization

Interconnects within IC packages and on PCBs together determine the overall product’s performance because the physical characteristics of these interconnects (length, cross-section, geometry, location) together determine how fast a high-speed signal can travel through all of them (see signal integrity). That is critical since performance is one of the most important requirements of the overall electronic system, and interconnects impact clock rate, timing budget, power distribution, thermal management, and more. Yet, the optimization of these interconnects today is done separately in silicon chips, IC packages, and PCBs. The individual design teams work in separation, and therefore, there is no communication or collaboration between them. But chiplets and SiPs offer an opportunity to change that due to the following:

  • Chiplet design time is shorter than the SoC chip because chiplets implement less functionality and are physically smaller
  • SiP package design time is shorter than the SoC package because of the reuse of the existing chiplets for standard functions with design-specific chiplets
  • SiP interposer and PCB interconnect signal integrity issues are similar and are managed with the same simulation methodologies

The result is that the design time of a SiP is getting ever closer to the design time of a complex PCB that uses SiPs. This, in theory, allows simultaneous co-design and interconnect optimization across new chiplets (IO buffers and micro-bump locations), chiplet arrangement in SiP (interposer), SiP/PCB interconnects, and PCB interconnects. The objective would be to get the highest possible performance for the entire interconnect implementation instead of maximizing a specific performance in a specific part of the implementation. Therefore, here’s where the biggest opportunity emerges:

Designing on all electronic interconnect implementation levels simultaneously while interactively negotiating and optimizing constraints within those levels to ensure that specific performance requirements will be met collectively.

This optimization should be done with the awareness of how the other SiPs are designed and interconnected on the same PCB.

Abstracting out the complexity

PCB designers continue working today with manual layout tools (although heavily assisted with automation algorithms) for component placement and trace routing geometries. However, the chip design industry left silicon geometry details a long time ago to the 100% automated image synthesis from the code generated by Hardware Description Languages (HDL) such as Verilog or VHDL. If the chip industry could do it, why can’t the PCB industry do it from a schematic or some other high-level system model?

I suspect that the PCB design tool vendors were missing an incentive because they did not have co-design optimization capability across all interconnect domains.

Electronic netlist and a digital thread

An electronic netlist is a list of named signals where each signal identifies all named nodes through which the signal travels. It is a special case of digital thread inherent to every electronic design. Among other things, a netlist enables the management of performance requirements realized by the physical implementations of the interconnects. However, because of the isolation of the chip, IC package, and PCB design processes each relies on incompatible domain-specific netlist data model. That disconnect prevents a unified system-level view of the entire electronic interconnect across all implementation domains.

Without traceability between these individual netlist digital threads, it is not possible to map high-level system model functionality and performance across all abstraction and implementation domains. It is also not possible to do that simultaneously while negotiating and optimizing the overall performance and the constraints per domain (again: chiplets, interposers, SiPs, and PCBs).

PLM-managed digital thread

Now imagine that an all-encompassing PLM-managed digital thread (data and process) can model electronic netlist traceability across all interconnect domains and do that in the context of the overall system model. A model that includes traceability to mechanical, embedded software, and wiring harness parts of the design since they, too, impact system performance. And combine that with traceability to all related Simulation Processes and Data Management (SPDM) information and Artificial Intelligence (AI) analysis based on Large Language Models (LLM) services. You can see how the entire electronic physical packaging design (chiplets, IC packages, and PCBs) could then be automatically optimized and implemented from a high-level system model abstraction. Again, think of a silicon design in VHDL/Verilog languages with 100% automated synthesis of the physical details.

An AI/LLM connection is critical to this vision. I shared some thoughts on that in my previous blog, The Future of Product Innovation and PLM – Abstraction, Digital Threads, and Artificial Intelligence.

EDA’s disruptive future

I know this is not how today’s Electronic Design Automation (EDA/ECAD) tools work. But they could be because of the advancements in silicon chiplets, SiP packaging, IC manufacturing, and the modern PLM-managed digital thread platforms. If they did, it would provide immense disruptive benefits to the industry by decreasing design time and costs, reducing functional product failures, and increasing manufacturing yields. What is the chance of that happening? Quite real. Judging by the various mergers and acquisitions between the related electronic design tool vendors, the electronics aspect of it may be closer than we think:

Digital transformation and Digital Engineering are already part of the regulatory environment through initiatives like the Department of Defense DoDi 5000.97 and the European Union Digital Product Passport (DPP). Do you know of any other disruptive trends resulting from Digital Engineering?

Related:
IC IC chiplets integrated circuits LLMs MBSE PCB printed circuit boards simulation and process data management SiP SPDM
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Aras Insights Artificial Intelligence Customer Stories Digital Engineering Digital Thread Digital Transformation